JTAG Programming: Using SuperPro IS01 and IS03 JTAG Programmers

Most MCU, CPLD and FPGA manufacturers such as Altera, Lattice, Xilinx, Atmel, ST and TI incorporate boundary scan logic (JTAG port) to their components to program devices in-system. JTAG interface is used by Xeltek SuperPro IS01 programmer to transfer data into non-volatile programmable memory such as CPLDs, flash and MCU chips. Volatile memory chips such as FPGA can also be configured in-system using the JTAG port.

Many JTAG devices can be chained together to form a JTAG chain. Parallel chips that do not have a JTAG interface can also be programmed using SuperPro IS01 and SuperPro IS03 programmers. Communication is done via an intermediate CPU chip to which the parallel flash is interfaced.

Advantages of using SuperPro IS01 and SuperPro IS03 for JTAG programming:

  • Multiple PCBs can be programmed at the same time using SuperPro IS01 cluster set up or SuperPro IS03 Gang programmer
  • Compact size, ATE port and DLL support help simplify ICT fixture / ATE integration
  • LabVIEW software driver support (Plug and play operation!)
  • PC mode as well as standalone mode operation (no PC needed)
  • Apart from JTAG, other interfaces supported are I2C, SPI, UART, BDM, MW, CAN and RS232
  • chips already supported on SuperPro IS01
  • High speed serial programming in accordance with IC manufacturer specifications
  • Powerful software with advance features such as production mode, serialization and programming speed control.
  • Multiple programmers can be connected to a single PC using a USB hub for mass production

SuperPro IS01 programmer comes with color coded ISP (In system programming) cable. This color coded cable can be connected to the JTAG port of target PCBs to program the device in circuit.

The connector pins of JTAG interface are:

  • TDI (Test Data In): Used to shift data and instructions in internal registers of a chip.
  • TDO (Test Data Out): Provide data output from Boundary scan register or other internal register of JTAG compliant chip.
  • TCK (Test Clock): TMS and TDI are sampled on rising edge whereas TDO is sampled at falling edge of TCK.
  • TMS (Test Mode Select): It determines the state of a TAP (Test access port) controller. TAP controller is a 16 state machine added to the chip and it is the heart of JTAG communication.
  • TRST (Test Reset) optional: (Active low) Asserting it places the chip in normal mode of operation.

VCC and Ground signals can be supplied by Xeltek SuperPro programmers (up to 5W). It is recommended an external power supply to be used for larger boards. For more tips on in-circuit programming, please refer to Tips of In-circuit programming.

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